The present invention relates, in general, to the field of dynamic random access memory (DRAM) integrated circuit (IC) devices and devices incorporating embedded DRAM. More particularly, the present invention relates to a dual bit line precharge architecture and method for low power DRAM.
Lower power consumption is a major design goal for today's integrated circuit memories. Many applications for memory devices are mobile and the ability to provide extended battery life can be a key market advantage. Nevertheless, for applications not utilizing battery power, power consumption can also be important. Power consumption leading to heating problems can add extra expense to systems by way of requiring the use of cooling fans or larger heat sinks. High power consumption in memory circuits may also require the system to operate at reduced clock frequencies. Overall, the cooling and total energy costs of data centers or server farms required for large internet or database management companies needs to be reduced. The amount of power attributable to the DRAM in these applications is a significant portion of the total, usually more than 50% of the total power of the system.
By the nature of their operation, DRAM memory devices require a precharge function. This involves bringing all the bit lines in a sub array to a fixed voltage such as VCC (e.g. a supply voltage level; as used herein, the voltage level “VCC” is also intended to encompass VBLH [voltage bit line high] which is typically near VCC), VSS (e.g. a reference voltage level or circuit ground), or VCC/2 when the sub array is not “active”. When both the bit line and the reference bit line (or bit line bar) are set to this precharge voltage, then the word line can go “active” allowing the charge from a selected memory cell to be placed on the bit line so that data can be sensed. Currently VCC/2 precharge is common in the industry for the bit line precharge voltage. This has the advantage of allowing low current consumption or low power operation due to the shorting together of bit lines as the sub array is entering precharge. Use of this shorting technique prevents current flow out of the VCC power supply and the precharge power is minimized. The non VCC/2 bit line precharge DRAM approaches do not have this power advantage and consume roughly double the memory array current or power as those utilizing VCC/2 precharge. There is also a di/dt (change in current per unit time) or power spike advantage for VCC/2 designs. For both the sensing portion and the precharging portion of the DRAM cycle, the power spike and related noise issues are approximately double for non-VCC/2 approaches.
However the voltage level of VCC is being reduced with each DRAM generation. Power supplies have been reduced from 3.3 v to 2.5 v, to 1.8 v to 1.5 v with each new Joint Electron Devices Engineering Counsel (JEDEC) standard, for example SDR (single data rate), DDR (double data rate), DDR2 (double data rate 2) and now DDR3 (double data rate 3) devices. This voltage reduction is also intended to save device operating power which is defined as:Power(watts)=V(volts)×I(amps)
Since current is a function of the operating voltage, by lowering the supply voltage power is reduced by the lowered voltage squared. The problem for DRAMs is since transistor threshold voltages cannot be reduced beyond a certain point and remain fixed in the 600 mV range due to fundamental physics of silicon, these reduced VCC voltages when divided in half do not allow for normal operation of complementary metal oxide semiconductor (CMOS) memory array control circuits. In particular, the bit line sense amplifiers run out of operating margin and cannot function properly when the percentage level is near the transistor threshold voltage level. For this reason some future DRAM designs are investigating non-VCC/2 bit line precharge levels for these new lower voltage standards.
Generally, what is needed is a memory circuit architecture and technique with the low voltage operation of non VCC/2 precharge and the low memory array current consumption of VCC/2 precharge. Additionally, what is needed is a memory circuit design with the low voltage operation of non VCC/2 precharge and the low memory array noise spike of VCC/2 precharge.